operating system os

OS Memory Mapped Input/Output

« Previous Tutorial Next Tutorial »

To communicate with the Central Processing Unit (CPU) each controllers has a few registers.

Many devices have data buffer that the OS can read/write.

The central processing unit (CPU) communicates with control registers and device data buffers in two ways discussed here one by one. Now let's talk about the first way.

Each control register is assigned the input/output port number. The special instruction like


the central processing unit can read register PORT and store the result in central processing unit register REG.

Similarly, the special instruction like


the central processing unit can write the contents of REG to a control register.

Including all the mainframe computers and most early computer worked in this way.

In this way, the address space for memory and input/output are different as shown in the figure given below:

memory mapped input output

Now, the following two given instruction

IN RO, 4



are totally different in this design.

The first instruction, that is,

IN RO, 4

reads the contents of the input/output port 4 and puts it in RO whereas the second instruction, that is,


reads the contents of the memory word 4 and puts it in RO.

Now, let's talk about the second way that how the CPU communicates with the control registers and device data buffer.

The second way introduced with the PDP-11, is to map all the control registers into memory space as shown in the figure given below:

os memory mapped io

Here in this case, each control register is assigned a unique memory address to which no memory is assigned.

This system is called as memory-mapped i/o or memory-mapped input/output.

Generally, the assigned address are at the top of address space.

The figure given below shows a hybrid scheme with memory-mapped input/output data buffers and separate input/output ports for control registers.

memory mapped io operating system

« Previous Tutorial Next Tutorial »


Quick Links
Signup - Login - Give Online Test